1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device by use of, e.g., a single damascene method or dual damascene method, and a substrate processing system used for manufacturing a semiconductor device.
2. Description of the Related Art
In semiconductor device manufacturing processes, a dual damascene method is frequently used for forming interconnection lines embedded in trenches and/or connection holes (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2002-83869). FIGS. 1A to 1I are explanatory views schematically showing a method of forming a Cu interconnection line, using a conventional dual damascene method.
At first, for example, an interconnection layer 500, an inter-level insulating film 501, and an anti-reflective coating 502 are formed in this order on a substrate. Further, a first resist film 503 is formed on the surface of the multi-layer structure thus formed (FIG. 1A). Then, patterning of the first resist film 503 is performed by a photolithography technique to form a predetermined pattern (FIG. 1B). In this patterning step, the first resist film 503 is subjected to light exposure with a predetermined pattern, and the light-exposed portion is selectively removed by development. Subsequently, the anti-reflective coating 502 and inter-level insulating film 501 are etched by an etching process using the first resist film 503 as a mask. Consequently, a connection hole 504 is formed to extend from the surface of the multi-layer structure to the interconnection layer 500 (FIG. 1C).
Thereafter, for example, the first resist film 503, which is not necessary any more, is peeled and removed by an ashing process (FIG. 1D). Then, a new second resist film 505 for forming an interconnection groove is formed (FIG. 1E). Then, patterning of the second resist film 505 is performed by a photolithography technique (FIG. 1F). Then, the anti-reflective coating 502 and a part of the inter-level insulating film 501 are etched by an etching process using the second resist film 505 as a mask. Consequently, an interconnection groove 506 is formed to be connected to the connection hole 504 and wider than the connection hole 504 (FIG. 1G). Then, the second resist film 505, which is not necessary any more, is peeled and removed (FIG. 1H). Then, the connection hole 504 and interconnection groove 506 are filled with Cu material, so that a Cu interconnection line 507 is formed (FIG. 11I)
Incidentally, with a decrease in size of semiconductor devices, the parasitic capacitance of inter-level insulating films has become an important factor to improve the performance of interconnection lines. For this purpose, low dielectric constant materials (Low-k materials) are used as the material of inter-level insulating films. In general, materials including alkyl groups, such as methyl groups, as end groups are used as low dielectric constant materials (Low-k materials) for forming inter-level insulating films.
However, according to the conventional damascene process described above, when a resist film is peeled, the inter-level insulating film 501 made of a Low-k material is damaged. This damage increases the dielectric constant of the inter-level insulating film 501, and deteriorates some effects obtained by using the Low-k material.
In order to minimize such damage as far as possible, it has been proposed to perform high temperature ashing by use of He gas and H2 gas for resist peeling, by A. Matsushita et al. “Low damage ashing using H2/He plasma for porous ultra Low-k”, Proceeding IITC 2003 pp 147-149. However, this technique is insufficient not only in the effect of suppressing damage but also in the effect of peeling resist, and thus is unpractical.